A Test Program Fault Simulator for Microprocessor Software-Based Self-Testing

• Main Authors: Jiang-Jung Wu, 吳佳龍
• Other Authors: Jiun-Lang Huang
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/93626535914953767835

碩士 === 國立臺灣大學 === 電子工程學研究所 === 93 === Software self-testing for embedded processor cores based on their instruction sets is a topic of increasing interest. Since it provides an excellent test resource partitioning technique for sharing the testing task of complex System-on-Chip (SoC) between slow, inexpensive testers and embedded code stored in memory cores of the SoC. Although BIST or scan chain can provide higher fault coverage for complex SoC, higher power consumption and area overhead are two issues that should be solved. Software self-testing concept is to utilize the instruction sets provided by microprocessors or microcontrollers. The users can establish test program candidates by combining the instructions. Users can perform logic simulation and detect structural faults with test program candidates, record the signals in every clock cycle at the same time. The signals which were recorded in every clock cycle are called test vectors. The purpose of proposed fault simulator is to transfer test vectors into test file like STIL (standard test interface language) which can be accepted by fault simulator, and evaluate fault coverage, fault dictionary with circuit files. In the thesis, we present a high accuracy fault simulator for user defined test program candidates to evaluate fault coverage by performing fault simulation without modifying the original design. We acquire some useful information like fault coverage, fault dictionary through fault simulation. Users can compare the quality of these test program candidates and find out which candidate can detect the most faults. In addition, higher fault coverage could be achieved by combining test program candidates or finding some specific ordering. Some experiments are established to validate the proposed fault simulator. The Parwan and 8051 IP cores are taken for experiments. Some test programs come from public literature and others are from public websites. Before performing fault simulation, the correctness of function was validated in the beginning. Simulation results are shown to validate the proposed technique.