Design of a Multi-bit Lowpass Delta-Sigma Modulator with Data Weighted Averaging Technique

• Main Authors: Hao-Yuan Siao, 蕭皓元
• Other Authors: Wan-Rong Liou
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/77491138833065779636

碩士 === 國立臺灣海洋大學 === 電機工程學系 === 93 === A high-resolution oversampled multi-bit Delta-Sigma modulator is designed in this paper. The 2nd-order multi-bit modulator can achieve 14-bit resolution of 24KHz signal bandwidth when oversampling rate of 128 is used. Fully differential switched capacitor is used to accomplish the modulator. The quantizer is made by a 17-level Flash ADC. Although multi-bit Delta-Sigma modulator has a lot of advantages, capacitor mismatch caused by process variation may induce nonlinearity of the DAC in the feedback loop and increase noise in signal band. Dynamic element matching technique is used to minimize the capacitor mismatch problem. Data weighted averaging (DWA) provides noise shaping for the nonlinear error. The DWA circuit is easy to be implemented. Hence, this technique is suitable for the multi-bit Delta-Sigma modulator design. The modulator with DWA technique is accomplished in this thesis. With the assistance of DWA technique, when the capacitor mismatch becomes worse, the SNR improved by data weighted averaging method becomes more apparent. DWA can increase SNR by 30dB when capacitor mismatch is 1% symmetrical linear gradient distribution. In this thesis, SNR improvement with DWA technique is studied on several different capacitor mismatch distribution functions, such as random, linear, and curved distributions. The circuit simulation work is done with HSPICE.