Test Integration of Core-Based System-on-Chip Supporting Delay Test
碩士 === 國立清華大學 === 電機工程學系 === 93 === The advent of deep-submicron semiconductor technology makes system-on-chip (SOC) possible. In order to handle the complexity of design methodology, intellectual property (IP) reuse is broadly adopted. However, the reuse of IP cores leads to challenges in test inte...
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| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/37094158785893919868 |