| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 93 === In the recent years, wireless product has been wildly used in many applications owing to the convenience for users. Such great desire also makes enormous progress in this field. In order to lower the cost and power, CMOS monolithic transceiver is the most potential candidates for achieving this tough work.
Frequency synthesizer is one of the most important building blocks in an integrating transceiver. In the past decades, delta-sigma fractional-N phase locked loop is the most widely used structure for solving the tough task of high frequency, small channel spacing and high spectrum purity which must be faced for synthesizer used in wireless application. In this project, a “DDS based syntheiszer” is proposed and implemented in UMC .18 um. This structure maintains both the advantages of direct digital synthesis (DDS) and integer-N PLL, besides it also gets rid of trade-off between channel spacing and settling time in conventional PLL.
In this project, the chip of this synthesizer contains a monolithic VCO, dividers, single sideband mixer, phase frequency detector and charge pump. The DDS and loop filter are provided externally. This thesis can be mainly divided into three parts; the first part is the system level analysis, which includes frequency plan and noise properties of the blocks in synthesizer. The second part is about circuits design. VCO will be discussed in details and other building block will also be considered. The chip implementation and measurement will be shown in the last part. This chip is implemented in UMC .18um. The chip size is 1.18mm X 1.05 mm.
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