| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 93 === Multiple-clock-domain (MCD) based a System-on-Chip (SoC) is the trend in modern ICs. With proper use of the technique of MCD, performance and power can be effectively optimized. In this thesis, we propose an MCD design methodology for the Advanced High-Performance Bus (AHB) of the Advanced Micro-controller Bus Architecture (AMBA) system. In the proposed methodology, a wrapper is developed for the AHB bus without any modification of the original core. Our wrapper adopts a handshaking mechanism, so we can guarantee that there is no data loss when communication is done between two different clock domains. In addition, the double flip-flop synchronization method is adopted in our wrapper to avoid the metastability problem. We also propose a FIFO synchronizer for some special architecture design, e.g. the AES engine developed in our lab. A dual-port RAM is
included to safely pass data across two clock domains. In our experiment, the hardware cost of the wrapper circuit is about 2.7K gates, while it can double the throughput of the RSA function by our MCD design. The FIFO synchronizer improves 25\% performance for the AES engine.
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