Studies on the Fabrication and Analysis of Single Poly Flash Memory

• Main Authors: Wei-Hsin Chen, 陳維新
• Other Authors: Huey-Liang Huang
• Format: Others
• Language: en_US
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/84317935965879114457

碩士 === 國立清華大學 === 電子工程研究所 === 93 === Non-Volatile Memory has been developed for a long time. It is more attractive in these days because the flash is necessary for more and more consumer application. Now, some structures of Non-volatile memory were invented like Split gate flash and stack gate flash and they are popular in production. They are fabricated with double poly process which is special for flash .It is more expense than the general CMOS process because of the longer process turn around time, lower yield and higher cost. In this thesis, single poly flash cell is introduced .It is CMOS compatible and available for technology of 0.25 um logic single poly process without any process change. Fowler Nordheim tunneling and Channel Hot Carrier injection are used in this structure. There are excellent performances of program and erase and useful duration ability. Besides, a good couple ratio trend is extracted from experiment and it can be the reference of cell size design and the correction reference of simulation. And a new application of RPO mask is reported. RPO mask improve the salicide process to prevent from the leakage path induced by the salicide. Single poly cell can be used in OPT or MTP application and will be widespread used for design-in step and replacing the mask Rom to shorter the turn-around time because of its low cost and logic CMOS compatible.