Folding and Interpolating A/D Converter Design
碩士 === 國立清華大學 === 電子工程研究所 === 93 === In this thesis, an 8-bit folding and interpolating analog-to-digital converter (ADC) that converts at 10 MHz is simulated and implemented in 0.35- m CMOS technology. The digital error correction and the decoder techniques by multiplexer are presented in this thes...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/73330365472364671679 |