| Summary: | 碩士 === 國立清華大學 === 資訊工程學系 === 93 === The RISC architecture is a load-store architecture that its data processing operations execute only on registers. When the programmer executes the computational operations, the processed data must be loaded from memory to registers and calculated. After completing the operations, it also needs to write the results back to memory. In fact, the signal processing application requires many data computations. It takes many resources to execute data movements and operations. Therefore, the performance of the signal processing application is limited on traditional RISC architecture. The proposed thesis will only focus on one RISC microprocessor because many microprocessors are RISC architecture, such as SPARC, MIPS, PowerPC and ARM. Furthermore, many signal processing applications are computation intensive, such as G.729 and MP3 codec. The proposed thesis also focuses on one signal processing application. In this thesis, ARM processor and MP3 decoder are selected as the RISC architecture platform and signal processing application, respectively. Moreover, because the signal processing application can not execute efficiently on traditional RISC architecture, both software optimization and architecture enhancement will be used to improve the performance of the system. The experimental results have shown great performance improvements in the system.
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