| Summary: | 碩士 === 國立清華大學 === 工業工程與工程管理學系 === 93 === Abstract
A number of inspection and measurement stations are set in the fabrication process to ensure that the quality of wafer meets the requirement. Because of the limited capacities and costs for in-line wafer inspections, only certain wafers are inspected among a specific number of lots.
However, conventional semiconductor wafer fabs meet a variety of economic challenge. The combination of shrinking devices geometries and increasing interconnect levels rapidly increase process complexity, which leads to higher manufacturing costs and longer cycle times.
Although there are many existing studies for IC sampling strategy in defect inspection, little research has been done the issue of metrology sampling. In-line metrology was real time to inspect the WIP. Currently, the sampling metrology numbers and sampling frequency are decided via the engineers’ experience. Thus, different engineers may build various sampling strategies.
This study aims to determine the optimal sampling strategy by developing a risk-based heuristic for statistically determining the sampling strategy for in-line inspection in wafer fabrication. For general defect inspection in wafer fabrication, Nurani et al. (1996) defined five parameters of sampling strategy including layers to be monitored, frequency for lots, and number of inspection wafers per lot, percentage area of the wafer and pixel size. However, for metrology inspection, we combine forth and fifth parameter to another parameter called number of dies in a wafer. Except layers to be monitor, our sampling strategy considers acceptance sampling plan in a wafer and a lot and sampling frequency that tradeoff the various risk (i.e., the aggregation of cost and probability) under different lot size.
Keywords: Bayesian decision analysis, sampling strategy, metrology, inspection, quality control
|
|---|
