| Summary: | 碩士 === 國立中山大學 === 電機工程學系研究所 === 93 === A improved less area 6-bit 3.3V SAR pipelined ADC is proposed. In this work, a 3-bit ADC is designed by the improved TIQ technology and flash like SAR ADC selection scheme. With the proposed TIQ method, it cancels the reference voltage generators and the backend encoders to reduce the area cost, besides the flash-like SAR ADC selection scheme makes the ADC still operate at high speed. The new 3-bit DAC in the MDAC is completed only by MOS transistors which channel widths and lengths are only adjusted to form each DAC output-voltage levels rather than using of resisters and capacitors in voltage mode. By the method, the area of the new DAC is reduced. By combining the proposed 3-bit ADC with the proposed 3-bit MDAC, an improved 6-bit ADC with less area is designed. By the TSMC 2P4M 0.35µm CMOS process, the area of the ADC is less than 0.017mm . The work shows that the power consuming is 3.77mW, the sampling rate is 160MS/S, the DNL is 0.344, and the INL is 0.74.
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