| Summary: | 碩士 === 國立高雄第一科技大學 === 電腦與通訊工程所 === 93 === This thesis presents analog and digital conversion with low-power architectures, which including 8-bit weighted-current digital-to-analog converter (DAC) and 6-bit analog-to-digital converter (ADC). In 8-bit weighted-current DAC, we improve the traditions weighted-current DAC architecture by changing the input driving time and then to reduce glitches. The current source employs different wide length ratio of PMOS to provide different weighted-current. The DAC has maximum differential nonlinearity error of 0.5LSB the power consumption is only 5.18mW and speed is 120MHz in simulations. In 6-bit analog-to-digital converter, a new kind of flash ADC is designed. In the first MSB 4-bit circuit, we use CMOS inverter rather than comparator, which can save core size and improve speed. By changing the threshold, each inverter can detect a particular input level, and convert the analog signal to digital. The next LSB 2-bit is converted from the result of MSB 4-bit output code and a new structure to find residual signal level. The ADC has maximum differential nonlinearity error of 0.5LSB the power consumption is only 13.22mW when the speed is 100 MHZ. Two chips are implemented by TSMC 0.35um CMOS process and now are realized through CIC education process to make samples.
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