| Summary: | 碩士 === 國立東華大學 === 電機工程學系 === 93 === In the present system on chip (SOC) designing, the designers exploit cores or intellectual property (IP) to implement the whole highly complex chip. During the process of integrating those systems, the interconnection also called network on chip (NOC), is one of factors that affects the performance and power consumption in chips. For the request of communication bandwidth on data link inside the interconnection, the data link has been one of sources in power consumption, and it is paid attention in constraints of designing by the chip designers. Therefore, reduce the power consumption can be achieved by controlling the bandwidth on data links.
This thesis developed the control policy on bandwidth controlling which is aimed at data link for on-chip network. It mainly exploits dynamic voltage scaling (DVS) to adjust the bandwidth on data link, an appropriate work point (operating frequency and voltage) will be chosen in the proposed method. Restated, this control policy choosing work point is based on one controller and two detectors: traffic detector and error detector. The controller chooses the work point by the response of the detection from those two detectors, and the choosing method is that predicts the appropriate work point for next observing window.
The proposed scheme exploits VHDL to implement the whole control policy scheme to prove that it has capability to reduce power dissipation, and compares the situation in different data width inputs in simulation.
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