A Critical-Path-Based Pipelined Scheduler for Video Processing Applications－Minimization of Response Time and Number of Processor

• Main Authors: Chia-Hung Chen, 陳嘉宏
• Other Authors: Mau-Tsuen Yang
• Format: Others
• Language: en_US
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/66376130676078946485

碩士 === 國立東華大學 === 資訊工程學系 === 93 === For video processing applications, response time is also an important requirement instead of throughput. An automatic Critical-Path-based pipelined scheduler is designed to minimize the response time and the number of processor needed under a desired iteration period. We design a two-phase algorithm. In phase one, we take a video processing application represented by a directed acyclic graph (DAG) and a desired iteration period (the reciprocal of throughput) as input. The objective of phase one is to minimize the response time under a given iteration period with critical path node first in a dynamic critical path (DCP) fashion. In phase two, the inputs are the partial schedule and the response time determined in phase one. The objective of phase two is to minimize the number of processor needed within the response time determined in phase one. The dynamic fashion of dynamic critical path is fit to our dynamic fashion of assigning new processor to the designated pipeline stage. The problem occurs in the parallel processing scheduling based on critical path heuristics is also encountered in our proposed algorithm. In the experiment results, the dynamic critical path heuristic is shown to be better than critical path heuristic.