| Summary: | 碩士 === 國立東華大學 === 資訊工程學系 === 93 === With advance of semiconductor technology, the designers can integrate more silicon IPs into a single chip than ever. Many studies predict that a single chip will accommodate up to 1 billion transistors in the end of this decade. Current SoC designs use dedicated wires or shared buses to connect IPs. Such communication infrastructures are unsuitable for the billion-transistor due to their limitation. To deal with the interconnect problems in SoC, a new methodology called network-on-chip (NoC) has been developed for the next-generation SoC paradigm. Regular tile-based NoC architectures have been proposed for interconnecting the IPs in SoC design. Such on-chip interconnection networks provide a high-performance chip-level communication infrastructure with regularity and modularity.
In this thesis, the design of a hybrid switch for on-chip networks in SoC design is proposed. This switch provides both guaranteed and best-effort communication services. We use the pre-scheduled circuit-switched architecture to support guaranteed service. Since the communication paths are pre-scheduled, this architecture provides guaranteed transmission latencies. For fully utilizing the bandwidth of the links, we further incorporate the packet-switched architecture that employs distributed FIFO queues and look-ahead routing. Our design has been implemented using UMC 0.18 um technology. Our chip has an aggregate bandwidth of 5 × 434MHz × 64 bits = 139 Gbits/s. For the circuit switched mode, our switch can run at 909MHz and achieves 290 Gbits/s total throughput. Compared to existing designs, our switch provides high performance with a reasonable area cost.
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