| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 93 === When the efficiency of the speed with the very large-scale integrated (VLSI) circuit increases fast, there are more and more transistors in the unit area, because of these, the timing delay is promoted relatively. The accurate clock is necessary in chip design, especially the SOC (System-On-a-Chip Design ) is developed, however, there is often phase error or clock skew which generates asynchronous phenomenon in different sub-circuit blocks, and it always causes mistakes to affect accuracy of the system. In this reason, the phase locked loop (PLL) is used to correct the clock phase when the major clock inputs the sub-circuit, and it can lead the operation clock of the sub-circuit into the same clock phase.
The challenge in designing the PLL, besides the improvement of the performance like low jitter, fast locking, and low power consumption, the restrictions of fixed loop parameters make the normal PLL just used in the specific standards, and that reduces the applications of the PLL. The loop parameters such as loop bandwidth, phase margin and damping factor must be adjusted to minimize jitter and to guarantee stability. According to the restrictions of the PLL, this thesis employs formula derives to find the relationship between the loop parameters. Furthermore, we use time to digital converter (TDC), programmable current mirror (PCM) to design a PLL that has wide range applications. In the proposed circuit, the loop bandwidth can adjust in different states, and the fixed phase margin and damping factor can keep the stability of the PLL.
We use the TSMC 0.18μm 1P6M CMOS process with 1.8-volt supply voltage in this thesis. The input reference frequency is 5MHz-100MHz, the output operation frequency is 100MHz-1GHz, and the period jitter is less than 1.8% of the output frequency. The power consumption of the proposed PLL is 26.86mW at 200 multiplication factor, 1GHz operation frequency.
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