Design of CMOS Transmitter Circuit for 2.5Gbps NRZ Data Transmission

• Main Authors: shin-Syong Guo, 郭世雄
• Other Authors: Kuo-Hsing Cheng
• Format: Others
• Language: en_US
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/32504694479009763007

碩士 === 國立中央大學 === 電機工程研究所 === 93 === Design of CMOS Transmitter Circuit for 2.5Gps NRZ Data Transmission Abstract Under the development of the network and computer operated speed in recent years, a trend of data transmission and studying at high-speed serial communication is growing. It is pointed out that the high-speed serial link interface is replacing gradually the conventional parallel bus interface in large data transmission by the development of PCI bus from PCI 1.0 to PCI-Express. The serial link technique is used at the optical communication in the past. However, it replaces the high-speed parallel data bus. The serial link technique is the time division multiplex (TDM) and point-to-point technique. It means that the low-speed parallel signals are transferred to the high-speed serial signal at the transmitter end and the high-speed serial signal is transferred to the low-speed parallel signals at the receiver end. This thesis focuses on the application of wire communication or serial link data transmission interface and takes the specification of PCI-Express as the objective in implementation. This work uses the multi-phase clock to generate the serial signal. In the output driver end, there is a large influence on the signal integrity due to the transmission line effect. So, this work achieves the well impedance match by adjusting the load. This thesis implements the transmitter chip fabricated in a TSMC 0.18μm CMOS technology. The transmitter operates at 2.5Gbps with 1.8V supply and the chip area is 685μm×685μm. The whole chip power consumption is 91.24mW.