| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 93 === The rapidly-growing volumes of data in telecommunication network have rekindled interest in high speed optical and electronic device and system. The serial-link transceiver system such as optical transceiver system, PCI-Express, serial-ATA、etc.. Because serial-link transmission is less transmission line, the effect of EMI, chip cost and area will be reduced. The cable and Bus will be replace by high speed serial-link transceiver. Wherever high speed serial-link transceiver apply to optical transceiver system in internet, high speed PCI-Express data Bus in computer and serial-ATA in storage component, the bandwidth requirement is increase day by day. Therefore, it is important to research high performance, high speed, high integration, low power consumption, and low cost serial-link transceiver side.
The subject of this thesis is the design for optical communication system which conform SONET OC-192 specification. The transmitter comprises a clock multiply unit(CMU) and a data serializer which transfer 16 parallel 622.08Mbps data to a 9.9533Gbps serial data. The function of clock multiply unit (CMU) is designed for SONET OC-192. Its function is to synthesize a 8 phase 1.24416GHz output signal from a 622.08MHz reference source. The data serailizer is adopted two stage architecture to transfer 16 parallel 622.08Mbps data to a 9.9533Gbps serial data by multi-phase relation to achieve a low power consumption and low cost design. The circuit is designed by TSMC 0.18μm CMOS process. The supply voltage is 1.8V. Total power consumption is 435mW.
The bit error rate (BER) is an index of transceiver system in general. Because the data rate of the transceiver system is increased quickly, the high speed test equipment is very expensive. Built-in test only need to add a small area in chip to test the chip performance. Therefore, the cost of testing will cost down vastly. In this design, a pseudo random bit sequence (PRBS) generator generates a test code in to device under test (DUT). And then, tester receives data form DUT to generate corresponding PRBS code to test bit error rate by decision block and control unit. Finally, the counter counts the number of error. The circuit is designed by TSMC 0.18μm CMOS process. The supply voltage is 1.8V. The highest operation of the tester is suit for 16:1 40Gbps serial-link transceiver. The resolution of the test is 10-5~10-14. Total power consumption is 36mW in highest speed operation.
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