An improved fast motion estimation algorithm based on adaptively thresholding and architecture design

碩士 === 國立交通大學 === 電機與控制工程系所 === 93 === In present video compression standard, such as H.264 and MPEG4, the computation of motion estimation is most of total encoding computation. Thus, many fast algorithms for saving computation load have been proposed. The fast search algorithm saves a lot of compu...

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Bibliographic Details
Main Authors: Fang-Yen Chien, 簡芳彥
Other Authors: Lan-Rong Dung
Format: Others
Language:zh-TW
Published: 2005
Online Access:http://ndltd.ncl.edu.tw/handle/uujzk3
Description
Summary:碩士 === 國立交通大學 === 電機與控制工程系所 === 93 === In present video compression standard, such as H.264 and MPEG4, the computation of motion estimation is most of total encoding computation. Thus, many fast algorithms for saving computation load have been proposed. The fast search algorithm saves a lot of computation load comparing full search block matching algorithm. In this type of fast algorithm, the block matching algorithm based on diamond search has better performance. But there is unnecessary computation in those fast block matching algorithms. We have designed an early termination technique to save more computation load. This technique tries to avoid unnecessary search step with predicting result of motion estimation. This predictive result is the threshold of early termination technique. We use the relation of temporal domain to predict result in sequence frames. The threshold is set before starting motion estimation of next frame. Thus, this threshold has good adaptability in those different video cases. Because this early termination technique can save computation load without destroying motion estimation, it should be applied to different fast search block matching algorithm. We proposed a novel diamond search algorithm based on early termination. For encoding in real time, we also designed architecture of this novel algorithm to implement. To cope with low off-chip memory utilization and low power consumption, the proposed architecture has parallel schedule and special memory address generator.