A Full-Bridge Class-D Amplifier Using Sigma Delta Modulation

• Main Authors: Kang-Yuan , Chen, 陳鏗元
• Other Authors: Jwu-Sheng, Hu
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/369nxc

碩士 === 國立交通大學 === 電機與控制工程系所 === 93 === This thesis proposes a design of full-digital class-D amplifier using sigma-delta modulation. The class-D amplifier operating the MOSFET (or IGBT) in saturation mode has the advantages of smaller size and higher power efficiency over traditional class-A/B ones. The underlying principle of generating the switching command is to convert the input signal into an oversampled binary signal. Compared with PWM modulation, sigma-delta modulation produces less distortion, noise and number of switching. The design and stability analysis of digital sigma-delta modulation are studied in this thesis using both 1- and 1.5-bit quantization schemes. The results show that the 1.5-bit scheme further improves the noise shaping performance and switching number reduction. The digital sigma-delta modulator is implemented on an FPGA and a full-bridge power stage is constructed to verify the design method. The resulting experimental platform is able to achieve a stereo amplifier with 22.05KHZ audio bandwidth.