The Study and Improvement of Chemical Mechanical Planarization and Etching Process Induced Lithography Overlay Error Variation

• Main Authors: Feng-Yi Chen, 陳峰義
• Other Authors: Jen-Chung Lou
• Format: Others
• Language: en_US
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/56541436860659073618

碩士 === 國立交通大學 === 電機資訊學院碩士在職專班 === 93 === Lithography is the key step of IC manufacturing and directly influences the limit of critical dimension (CD).The lithography is to transfer the pattern on mask to wafer in right position, through alignment and exposure. The pattern misplacement between the layer and its previous layer is called overlay error. Once the overlay error exceeds the limit of fault tolerance defined by design rule will make circuit either open or short, and then suffers yield lost. Therefore, to minimize the overlay error and well to control the overlay error are always an important topic of lithography. In advanced IC fabrication, lithography is no longer the only factor resulting in the misalignment. In fact, such as chemical mechanical planarization (CMP), etch, and thin film deposition also influence the alignment and overlay significantly. In this thesis, we discuss the possible factors affecting overlay error, such as chemical mechanical planarization and etching process. Finally, we demonstrate the solution by unifying CMP rotary direction and increasing over-etching to achieve tighter overlay control. In conclusion, we discuss the wafer process that may influence alignment mark shape. Alignment improvement strategies reducing the sensitivity with wafer process is also provided.