| Summary: | 碩士 === 國立交通大學 === 電機資訊學院碩士在職專班 === 93 === At sub-90nm device nodes, implementation of shallow trench isolation (STI) becomes more challenging. One of the major challenges with scaling STI have to deal with is the STI-induced mechanical stress effect which impact MOSFET electrical behavior.
In this thesis, impact of shallow trench isolation (STI) induced mechanical stress on MOSFET electrical properties was investigated systematically by means of a full-matrix active area layout experiment in advanced 90nm CMOS process technology. Both the drive current, off current and threshold voltage variations as a function of the poly to STI distance are reported. From this experiment, an opposite trend is observed between n- and p-MOS with the presence of STI stress and transistor layout with different size of W and L has different sensitivity to STI stress. In addition, simulation of stress distribution with various active and STI dimensions was performed qualitatively for analyzing the stress trend in detail to verify the silicon electrical characterization of stress-dependent phenomenon. In particular, silicon device surrounded by silicon oxide exhibits compressive stress, which will be higher as the device dimension becomes smaller. Therefore, from this study, we demonstrate that stress effects can and should be taken into account in IC design phase in present and sub 90nm nodes CMOS generations.
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