Design on Power-aware Pipelined Multiplier Using Double Truncating Technique

• Main Author: 沈志遠
• Other Authors: 董蘭榮
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/41527666728164951944

碩士 === 國立交通大學 === 電機資訊學院碩士在職專班 === 93 === “Power awareness” is a new research in recent years. It is able to scale power and quality tradeoff. For example, consider the user of a digital camera. At times, the users might want high image quality at the cost of reduced battery lifetime. At other times, the user might want low image quality in return for extending battery lifetime. Such tradeoffs can only be optimal if the system was designed in power-aware manner. In this paper, we design a power-aware pipelined signed multiplier for DSP application. This multiplier has 16 bits multiplicand , 16 bits multiplier , and 16 bits product . We use the Dadda scheme and Brent-Kung carry look-ahead adder to present a fast multiplier implemented as a 6-stage pipeline register. We make double truncating technique to truncate both product and input (including multiplicand and multiplier) for power awareness. The design is written by VHDL and synthesized by Synopsys Design Analyzer. Power is estimated using Prime Power. We use Signal-Noise Ratio (SNR) to represent quality, and estimate battery lifetime by Battery Design Player. By the definition of lossy power awareness , we choose truncating way of Inputs remained Zero and Products remained Data(IZ-PD) and select 4 operation mode to propose optimal power-aware multiplier. The power-aware multiplier increased 37% battery lifetime to unpower-aware multiplier while lost 14 dB SNR and increased 3% area. Besides, the clock frequency achieved 156.25 MHz to be high speed multiplier.