The Impact of Interfacial Layer and the Halo Implant on the Reliability of High K Dielectric CMOS Devices

• Main Authors: Guan-De Lee, 李冠德
• Other Authors: Steve S. Chung
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/19384572148428672624

碩士 === 國立交通大學 === 電子工程系所 === 93 === With the scaling of gate oxide thickness into 1 nm regime, the gate leakage current will increase exponentially with reducing thickness. Several different methods can be employed to improve device performance and reliability. Among them, high K gate stack CMOS device is a good choice. Not only high K gate stack is needed, but also halo implant process for improving SCE ( short channel effect ) is inevitable. The impact of halo implant specifically on the edge of Hf based high K gate stacks are evaluated by a unique leakage measurement. Halo implants with large AMU ( Atomic Mass Unit ) through ALD ( Atomic Layer Deposition ) Hf based high K dielectric without appropriate IL ( interfacial layer ) may cause unavoidable damage at the gate edge region, which further causes serious degradation of the devices. In this thesis, extensive study and comparison have been carried out for various IL process with different halo implant species. First, a unique leakage measurement is made for different interfacial layer processes. They include nitrogen free, nitrogen incorporation by plasma and thermal, for the interfacial layers respectively. Next, we examine the influence of different halo implant species on each IL. It was found that halo implant impact on device characteristics, as a result of high K gate dielectric degradation, is strongly dependent on the halo implant species and governed by the IL used. Reliability test of these devices was then carried out in the latter half of this work. Because the effect of different halo implant on IL is not obvious during the Positive Bias Temperature Instability(PBTI) reliability testing, Gate-Induced Drain Leakage (GIDL) current and Gated Diode measurement are employed to observe the hot carrier stress effect. After the hot carrier stress, it was found that from the observation of Vt instability and Gm degradation results, optimized high K gate stack with even higher bombardment from the heaviest halo implant species exhibits better performance by comparing to the control oxide. These results provide an important guideline for the design of CMOS devices with high K gate dielectric.