| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 93 === Using voltage island methodology to reduce power consumption for System-on-a-Chip (SoC) designs becomes more and more popular recently. At present, this approach is mostly considered in system-level architecture. For hierarchical design and reuse intellectual property (IP) are widely used, it is necessary to optimize the floorplanning/placement considering voltage island generation to solve critical path delay problems, reduce area and wirelength, furthermore we can cooperate with the power management unit to attain low power consumption. Therefore we proposes in this thesis a low power floorplanning/placement methodology considering performance constraints and voltage island generation. Our method is flexible and can be extended to hierarchical application, and the experimental results show our method is effective to meet the performance constraints and reduce the power dissipation.
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