GA-Based Task Scheduling for Heterogeneous Network-on-Chip
碩士 === 國立交通大學 === 電子工程系所 === 93 === Network-on-Chip is a new design paradigm to meet the communication requirement of future billion-transistor System-on-Chip. In this thesis, we propose a genetic algorithm (GA) based task scheduling technique to schedule the applications to the heterogeneous Networ...
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ndltd-TW-093NCTU54280602016-06-06T04:10:40Z http://ndltd.ncl.edu.tw/handle/87954739342946786801 GA-Based Task Scheduling for Heterogeneous Network-on-Chip 基於基因演算法應用於異質性網路單晶片之任務排程方法 Wan-Hsi Hsieh 謝萬熹 碩士 國立交通大學 電子工程系所 93 Network-on-Chip is a new design paradigm to meet the communication requirement of future billion-transistor System-on-Chip. In this thesis, we propose a genetic algorithm (GA) based task scheduling technique to schedule the applications to the heterogeneous Network-on-Chip. The task scheduling process attempts to arrange the allocation of processor for each task such that the system throughput is maximized. As well, a new mating operator of GA is also proposed to improve the performance of traditional GA by considering the characteristics of application. The experimental results show that proposed mating operator not only outperforms traditional ones by 10% averagely, but also requires less computation time. Jing-Yang Jou 周景揚 2005 學位論文 ; thesis 48 en_US |
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碩士 === 國立交通大學 === 電子工程系所 === 93 === Network-on-Chip is a new design paradigm to meet the communication requirement of future billion-transistor System-on-Chip. In this thesis, we propose a genetic algorithm (GA) based task scheduling technique to schedule the applications to the heterogeneous Network-on-Chip. The task scheduling process attempts to arrange the allocation of processor for each task such that the system throughput is maximized. As well, a new mating operator of GA is also proposed to improve the performance of traditional GA by considering the characteristics of application. The experimental results show that proposed mating operator not only outperforms traditional ones by 10% averagely, but also requires less computation time.
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Jing-Yang Jou |
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Jing-Yang Jou Wan-Hsi Hsieh 謝萬熹 |
author |
Wan-Hsi Hsieh 謝萬熹 |
spellingShingle |
Wan-Hsi Hsieh 謝萬熹 GA-Based Task Scheduling for Heterogeneous Network-on-Chip |
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Wan-Hsi Hsieh |
title |
GA-Based Task Scheduling for Heterogeneous Network-on-Chip |
title_short |
GA-Based Task Scheduling for Heterogeneous Network-on-Chip |
title_full |
GA-Based Task Scheduling for Heterogeneous Network-on-Chip |
title_fullStr |
GA-Based Task Scheduling for Heterogeneous Network-on-Chip |
title_full_unstemmed |
GA-Based Task Scheduling for Heterogeneous Network-on-Chip |
title_sort |
ga-based task scheduling for heterogeneous network-on-chip |
publishDate |
2005 |
url |
http://ndltd.ncl.edu.tw/handle/87954739342946786801 |
work_keys_str_mv |
AT wanhsihsieh gabasedtaskschedulingforheterogeneousnetworkonchip AT xièwànxī gabasedtaskschedulingforheterogeneousnetworkonchip AT wanhsihsieh jīyújīyīnyǎnsuànfǎyīngyòngyúyìzhìxìngwǎnglùdānjīngpiànzhīrènwùpáichéngfāngfǎ AT xièwànxī jīyújīyīnyǎnsuànfǎyīngyòngyúyìzhìxìngwǎnglùdānjīngpiànzhīrènwùpáichéngfāngfǎ |
_version_ |
1718294480298180608 |