Dynamic Frequency and Voltage Management Design for Energy-Aware FFT Processor Application

• Main Authors: Lawrence, 吳健豪
• Other Authors: Wei Hwang
• Format: Others
• Language: en_US
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/27108314136953638207

碩士 === 國立交通大學 === 電子工程系所 === 93 === Using dynamic frequency and voltage management (DFVM) for a 1024-point energy-aware fast Fourier transform (FFT) processor is presented in this thesis. The energy-aware FFT processor allows for changing bit precision (8 bit or 16 bit) dynamically. DFVM scheme controls the frequency at 413Mz for 8 bit precision, 206Mz for 16bit precision which supply voltage is 1.8v. More advanced, the optimal energy delay product (EDP) point is that 1.2v supply voltage with clock frequency operates at 188Mz for 8 bit precision, 93Mz for 16bit precision. This optimization point save archive 54.7％ and 56.4％ energy dissipation, 18％ and 13％ EDP for fully 8 bit and 16 bit precision respectively. In DFVM scheme, the proposed clock switch circuit can prevent from the race problem when switch two different clock. The proposed voltage down converter (VDC) generates 1.2v supply voltage, only has temperature dependency of 1.1 mV / ℃ characteristic. DFVM and energy-aware FFT processor are implemented in 0.18-μm CMOS technology.