Simultaneous Power and Routing Cost Minimization in Scan Chain Design

• Main Authors: Li-Chung Hsu, 許力中
• Other Authors: Hung-Ming Chen
• Format: Others
• Language: en_US
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/99798713697142029579

碩士 === 國立交通大學 === 電子工程系所 === 93 === With advanced VLSI manufacturing technology in deep submicron (DSM) environment, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC design, circuit testability becomes one of the most challenging work. Among design for testability (DFT) techniques, scan-based built-in self-test (BIST) architectures are widely used in industry. However, without careful design in scan cell placement and chain ordering, circuits consume much more power in test mode operation than that in normal functional mode. This elevated testing power may cause problems including overall yield lost and instant circuit damage. In this thesis, we present an effective approach to simultaneously minimizing test power and routing cost in scan chain design after cell placement. The experimental results are encouraging. Compared with a recent result in [6], which uses the approach with clustering overhead, we obtain up to 10% power saving under the same routing cost.