| Summary: | 博士 === 國立交通大學 === 電子工程系所 === 93 === In this thesis, the design methodologies and implementation techniques of two double quadrature receiver front-ends for 5-GHz IEEE 802.11a wireless local area network (IEEE 802.11a wireless LAN) and low-voltage applications are presented. There are three parts in this thesis, including (1) the modeling, design, and analysis of the active polyphase filter; (2) the design and analysis of a 5-GHz double-quadrature receiver front-end for IEEE 802.11a wireless LAN applications; (3) the design and analysis of a 1-V 2.4-GHz double-quadrature receiver front-end for low-voltage applications.
At first, a new technique to implement the transfer function of polyphase filter with CMOS active components is proposed and analyzed. In the proposed polyphase filter structure, currents mirrored from capacitors and the transistors in a single-stage are used to realize high-pass and low-pass functions, respectively. The four-stage structure expands the frequency bandwidth to more than 20MHz. Furthermore, a constant-gm bias circuit is employed to decrease the sensitivity of image rejection to temperature and process variations. HSPICE simulations are performed to confirm the performances. With the current-mode operation, the low-voltage version of proposed active polyphase filters was designed. It can be operated at 1V power supply with similar performance but with only 50% of the power dissipation of the normal-voltage version. The proposed four-stage polyphase filter is fabricated in 0.25-�m CMOS 1P5M technology. The measured image rejection ratio is higher than -48dB at frequencies of 6.1MHz ~ 30MHz. The measured voltage gain is 6.6dB at 20MHz and the IIP3 is 8dBm. The power dissipation is 11mW at a supplied voltage of 2.5V and the active chip area is 1162×813µm2.
Secondly, a 5-GHz CMOS double-quadrature receiver front-end used for IEEE 802.11a wireless LAN is proposed. The receiver consists of a low-noise amplifier, an RF quadrature generator, double-quadrature mixers, a quadrature voltage-controlled oscillator, and an active polyphase filter. A new one-stage RLC phase shifter is employed to generate quadrature RF signals. Using the current reuse technique, double-quadrature mixers are merged with the quadrature VCO. The proposed active polyphase filter with four-stage structure is designed to reject the image signal. The receiver provides the advantages of low power dissipation, a small chip area, and a low sensitivity to parasitic components. The measured noise figure is 8.5dB and the gain in the channel bandwidth is above 16dB. The image rejection within the channel bandwidth exceeds 50.6dB and the IIP3 is –13dBm. Implemented in 0.18-um CMOS technology, the power dissipation of the fabricated double-quadrature receiver is 22.4mW at a supplied voltage of 1.8V and a die area of 2�e1.5 mm2.
Finally, a 1-V 2.4-GHz CMOS double-quadrature receiver is proposed and analyzed. The double-quadrature receiver comprises a new low-noise amplifier, a new RF quadrature generator, a quadrature voltage-controlled oscillator, double-quadrature mixers and an active polyphase filter. In the new 1-V low-noise amplifier, LC-tank is used to reject the common-mode signal. The LC-tank provides high impedance in the desired frequency and has almost zero dc voltage-drop. These characteristics make it suitable for high frequency and low-voltage design. A new one-stage RLC phase shifter is employed to realize the new RF quadrature generator where cross-couple transistors are used to generate a negative transconductance to decrease the output conductance and increase the load impedance. The gain of the RF quadrature generator thus can be enhanced and the power consumption can be reduced. The 1-V 2.4-GHz double-quadrature receiver is fabricated with 0.25-�m CMOS 1P5M technology. From the measurement results of the low-noise amplifier, the noise figure and common-mode rejection ratio are 5.5 dB and 29 dB, respectively. In the measurement of double-quadrature receiver, the measured image rejection ratio is higher than 30.2 dB at image frequencies of 2.43 GHz ~ 2.48 GHz. Furthermore, the measured voltage gain is 12 dB at 2.42 GHz and IIP3 is –12 dBm. The tuning range of voltage-controlled oscillator is 400 MHz. The power dissipation of the 1-V 2.4-GHz double-quadrature receiver is 34.6 mW at a supplied voltage of 1V and the active chip area is 1.8×1.6 mm2.
It is believed that the proposed two double-quadrature receiver front-ends can be applied to the design of high-performance high-frequency low-power high-integration all-CMOS wireless communication systems. Further research on the integration of other transceiver components will be conducted in the future.
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