Low Power Flip-Flop and Reconfigurable FIFO Design
碩士 === 國立交通大學 === 電子工程系所 === 93 === The clocked storage elements using the low power technique are realized in this paper. The low swing conditional capture edge-triggered flip-flop (LSCCFF) suitable for the low switching activity applications is proposed and simulated in TSMC 100nm technology. The...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/02946183355805823639 |