Investigation of Nickel Silicide Application toward Nano-Scale Device Technology

• Main Authors: Tsung-Lin Lee, 李宗霖
• Other Authors: Chung-Len Lee
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/698358

博士 === 國立交通大學 === 電子工程系所 === 93 === In advanced CMOS devices, as contact dimensions scale down to nanometer range, contact resistance of source and drain is increased correspondingly. As a result, the technique of metal silicides for poly gate and source/drain has been developed to reduce the contact resistance and the parasitic junction resistance as well. In nanometer MOSFET fabrication, this silicidation process requires considering to suppress short channel effect (SCE) when forming the ultra shallow source and drain junction. Therefore, metal silicides owning a perfect interfacial property with Si above an ultra-shallow junction is considered as a critical module toward the realization of nano-scale CMOS. Besides, as the oxide thickness scaling down with the device dimensions, the gate oxide reliability will also be a concern for the silicided gate process. The objective of this dissertation is to investigate the feasibility of nickel silicide integration into the formation process of the ultra shallow junction and full silicide gate. First of all, we have investigated the thermal stability of nickel silicide with Zr capping. To employ its good capability for the suppression of oxygen incorporation during silicidation process, a siginificantly improvement on the thermal stability of nickel silicide can be obtained. And a smooth interface between silicide and silicon also can be demonstrated by TEM images. Then, we combined the Zr capped on nickel silicide with the p+/n junction, and investigated the influence on junction charateristics by this capping layer compared with a conventional Ti-capped method. Due to the advantages of improvement on thermal stability, the increase of leakage current resulted from the silicidation process can be suppressed as expected. By the advantage of well-controlled silicide depth, an 30nm ultra shallow junction with nickel silicide was also accomplished as expected. Third, the formation of ultra shallow junction by PH3 plasma doped method was investigated. Its low surface concentration can be improved by a cap layer but meanwhile it will result in the increase of junction depth. In our experimental, a defect less ultra shallow junction formation by PH3 plasma doped can be achieved by short activation time. Finally, we have observed the behavior of nickel silicide gate based on different gate structures. By phosphorus incorporation, the gate oxide reliability can be enhanced. Thus, we believed that full nickel silicide gate still possesses potential for the application on future device fabrication.