Low-Power Address BUS Encoding

• Main Authors: Tsung Hsi Weng, 翁綜禧
• Other Authors: 鍾崇斌
• Format: Others
• Language: en_US
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/75285083062877223910

碩士 === 國立交通大學 === 資訊工程系所 === 93 === Reducing power consumption of computer systems has gained much research attention recently. In a typical system, the memory bus power constitute will over 50% of all system power; and this power is required due to bus signal transitions (0->1 or 1->0). Reducing the number of memory bus transitions is hence an effective way to reduce system power. I present encoding schemes to reduce instruction address bus, data address bus, and instruction/data mixed address bus power consumption. For instruction address bus, T0 with DAT (Discontinuous Address Table) is proposed to handle both consecutive addresses and the branch target addresses; for data address bus, combination of T0 and BI method, variable-stride, and SRWEC (Separated Read/Write Encoding Contents) is proposed to handle both the randomness and continuities of data address sequence; as for instruction/data mixed address bus, DAT is used for instruction address sequence and Stride-Table which can take use of the relationship between instruction address and data address is applied for data address sequence. Simulation results show that the overall bus line switching reduction is 90.5% of unencoded instruction address bus, 26% of unencoded data address bus, and 77.4% of unencoded instruction/data mixed address bus.