| Summary: | 博士 === 國立交通大學 === 材料科學與工程系所 === 93 === The scaling of the CMOS transistor has been the primary factor driving improvements in microprocessor performance. Transistor delay times have decreased by more than 30% per technology generation resulting in a doubling of microprocessor performance every two years. In order to maintain this rapid rate of improvement, aggressive engineering of the source/drain and well regions is required. One of the key factor for improving device performance is to select silicide for low resistance and shallow source/drain junction.
A compromising scheme, which uses silicide(metal)/polysilicon bi-layer structure as gate electrode and low contact-resistance interface, was investigated by many researchers. The incorporation of silicides in the devices structure is often implemented by using the self-aligned technique. The metals can react with silicon on both poly gate and source/drain area to form silicide. However, for the shallow junction requirements, the thickness of the silicide has to be controlled. The trade-off between low leakage at source-drain area and low resistance for gate stack needs to pay more attention on silicide material and process selection.
Cobalt silicide(CoSi2) meets many the criteria and has become one of the most promising candidates for silicide technology application. CoSi2 is used for source, drain, and gate in the submicron CMOS device is an attractive material because its potential for low resistance. The resistivity and thermal stability of CoSi2, are better than those of TiSi2. In addition, the sheet resistance of CoSi2, is relatively insensitive to decreasing line-width.
However, CoSi2 junctions can suffer high diode leakage because of non-uniform CoSi2/Si interfaces or CoSi2 spikes. The margin between the silicide thickness and junction depth lower range is getting smaller along device shrinkage, therefore good uniformity and smooth silicide/Si interface are necessary to serve deep sub micron process need in order to take care the needs from two ends - speed and power consumption.
In this thesis, cobalt silicide was applied on nano-scale CMOS process. Source/drain area, activation area resistors and poly resistors were formed with cobalt silicide and the behavior of silicide on CMOS devices and resistors were studied. According these studies, the capping material selection is very important for the cobalt silicide formation. The TiN capping and Ti capping processes demonstrated very different behaviors on resistivity for narrow line and junction leakage. Penetrated silicide profile in TiN capping process induced the anomalous width-dependent sheet resistance change. This penetrated silicide profile in TiN capping process also resulted in the anomalous junction leakage as compared to the junction leakage performance of Ti capping process. Besides the optimized capping material selection, the smooth CoSi2/Si interface can be achieved by implementing oxide-mediated epitaxy (OME) process. Low sheet resistance and junction leakage current can be obtained by optimal process.
Finally, the thermal stability for silicided poly resistors was studied. Anomalous thermal stability for narrow lines was concluded to related to the grain size distribution and the actual poly line width. The thermal stability for silicided poly resistors was also studied by extracting the activation energy for agglomeration. A quantitative equation for thermal stability was derived by the combination of thickness, line width and critical grain size. This equation shows good correlation with the activation energy of silicide thermal stability degradation and the material thermal stability index can also be derived
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