Improvement on the Gate Electrode Defect of Integrated Circuits using Designed Experiments

• Main Authors: Chia-Wei Hsu, 許家維
• Other Authors: Lee-Ing Tong
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/84105800443606610030

碩士 === 國立交通大學 === 管理學院碩士在職專班工業工程與管理組 === 93 === Semiconductor industry in Taiwan currently has faced strong competition from the wafer foundry companies in Mainland China, therefore, to retain its own competitiveness in the market, all the wafer foundry companies in Taiwan are dedicating their great efforts on the improvement of semiconductor manufacturing yield rate, it is hoped that the product yield rate can be enhanced in short term, this is especially true for manufacturers of DRAM. Currently, traditional experimental method is used in the industry to perform wafer defect analysis, that is , one factor is adjusted each time to conduct the experiment , this method does not guarantee that it can find the optimum solution, besides, it is a very tedious process; therefore, this study aims at using Randomized Complete Block Design (RCBD) method with three factors and two levels for each factor to improve the gate electrode defect of integrated circuits. The gate electrode defect forms as small bumps on the surface after WSix is deposited, it leads to serious circuit bridge after gate electrode circuit is completely manufactured. The wafer yield rate thus could drop by 3% at the worst case . Since the defect problems mentioned in this study are not yet investigated by literature over the world, therefore, there are very few information we can refer to. Transmission electron microscopy (TEM) was used and the gate electrode defect appears between the processes of polycrystalline silicon and WSix. Therefore, Three experimental factors affecting yield rate from the sectioning sample are : HCL/H2O2/ H2O (Hydrochloric Peroxide Mixture, HPM)mixed acid , oxide etch and polycrystalline silicon deposition. Experimental planning by setting the process parameters of HPM mixed acid as two levels of ”Using HPM” and ”Not using HPM”; setting the process parameters of oxide etch as two levels of ”HF vapor (100% HF)” and ”Dilute HF(H2O2: HF = 200:1)“ ; and setting the process temperatures of the polycrystalline silicon deposition as two levels of ”1050°C (high temp.)” and ”575°C (low temp.)” .The block variable is the plant area , it has two levels for the whole experimental planning, each experimental condition is performed 8 times. In the mean time, the Mintab statistical software is used for analysis, we eventually find an optimum recipe for solving the gate electrode defects, that is , ”use HF vapor (100% HF)for the oxide layer etching ”.By using the above optimum recipe in the mass production, we are able to obtain a stable yield tare of 82%~84%,it also help to make the company product more competitive.