A 1G Sample/s 6-bit Flash A/D Converter with Novel Bubble Tolerant Thermometer-to-Binary Encoder

• Main Authors: Yao-Jen Chuang, 莊堯仁
• Other Authors: Bin-Da Liu
• Format: Others
• Language: en_US
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/41148952535447500744

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 93 === 　　With the relentless advancement of process technology, mixed-signal circuit design has become an inevitable trend for system integration. Behaving as an interfacing bridge between digital and analog realms, A/D converter always plays a critical role. A high performance A/D converter can effectively improve the whole circuit performance. 　　 　　In this thesis, a 1 GHz 6-bit flash A/D converter is proposed. The main topic is focused on resolving coding errors induced by the bubble effect of thermometer-to-binary encoder. For addressing this issue we propose a novel bubble tolerant thermometer-to-binary encoder. In this design, each bit is encoded respectively according to the corresponding bits of thermometer code. Therefore the bubble effect can only reflect itself on the lower significant bits and thus the bubble-induced coding error can be suppressed. 　　 　　A 1GHz 6-bit flash A/D converter prototype has been designed for the verification of proposed encoder. Building blocks such as track-and-hold circuit, comparator, and offset-averaging network are discussed. The whole circuit is simulated and verified by using TSMC 0.18 μm 1P6M CMOS process spice model. Simulation results show the SNDR value for the proposed flash A/D converter is about 36.45 dB, equaling to 5.76 bits ENOB, under 324 MHz input signal and 1 GHz sampling rate. The total power consumption is 186 mW.