| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 93 === With the advance of deep submicron technology, the low power supply will become the trend of circuit development based on the consideration of circuit reliability. However, the signal dynamic range will be decreased as the reduction of supply voltage. In order to restore the dynamic range, we must suppress the noise and signal distortion. By this way, it will indirectly increase the power consumption of analog circuits. Especially, a high-gain op-amp must be required to guarantee the required accuracy in the conventional pipelined ADC design. However, due to the process limitations, it is difficult to implement such high-gain op-amp. The penalty of additional power dissipation must be usually paid to implement this op-amp. In this thesis, a technique called as modified time-shifted CDS is proposed to relax the requirement of high-gain op-amp in the pipelined ADC design. A 10-bit 100 MS/s pipelined A/D converter has been designed and implemented with the TSMC 0.18 �慆 CMOS 1P6M process. The power consumption of this chip is 100mW at 1.8 V, and the chip area is 2 mm2.
In addition to the chip design of pipelined ADC, a complete behavioral model including many non-idealities is constructed by Simulink tool. This model can be used to predict the performance of pipelined ADC, which can reduce the design time significantly. In addition, we can use this model to optimize power consumption of a pipelined ADC in behavior level.
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