Novel Scan Techniques for Low Power and Low Cost Testing
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 93 === With the progress of very large scale integration (VLSI) techniques, the circuit complexity increases dramatically. To enhance the testability of the circuit, many design for testability (DFT) techniques are developed. Scan technique is one of these technique...
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| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/53753819128553217409 |