| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 93 === With the progress of very large scale integration (VLSI) techniques, the circuit complexity increases dramatically. To enhance the testability of the circuit, many design for testability (DFT) techniques are developed. Scan technique is one of these techniques and is widely used in industry. However, excess power dissipation and large test cost are two critical problems of scan testing. The test cost is composed of three main factors, namely test application time, test data volume and the number of test pins.
In the power aspect, recently the multiple capture orders technique has been used to reduce both average and peak power dissipation. The technique, however, requires long test generation time. In this thesis, we propose a modified test pattern generation procedure to shorten the test pattern generation time.
Furthermore, we propose a novel scan technique to reduce the test application time, test data volume, and test power dissipation simultaneously. The basic idea is to analyze the compatibility of scan flip-flops and construct multiple scan chains with single scan input without any fault coverage degradation. This technique can be directly applied to the configuration of multiple scan inputs according to the number of available test channels. Besides, we also give a low power technique applied to our scan architecture. Experimental results for large ISCAS’89 benchmark circuits show that with single scan input, the proposed method can reduce the test application time and test data volume by 90%, and reduce power dissipation by 96.3% in average compared with conventional scan methodology.
As described above, we can efficiently reduce the test power dissipation and can reduce the test application time and test data volume without extra test pins. Hence, the two critical problems of scan testing can be solved.
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