| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 93 === Owing to the growing demand for GS/s level ADCs nowadays, a 6-bit single analog path 2 GS/s flash ADC is proposed in this thesis. This ADC is optimized to operate in high speed applications such as hard disk read channel and high speed communication system.
The proposed ADC architecture consists of a pseudo-differential open-loop track-and-hold circuit, a comparator array composed of 64 comparators and 16 dummy comparators, a four-channel 64-to-6 ROM-based encoder, and a clock generation and distribution system. Instead of traditional latch-based comparators, continuous-time comparators are employed to simplify block design and remove noises induced by switches and latches. Moreover, the preamplifiers and 1st stage comparators are averaged by using the resistive network technique.
This work is fabricated in TSMC 0.18-�慆 mixed signal 1P6M salicide 1.8V/3.3V CMOS technology. The chip occupies 3.57 mm2 die area and the digital part occupies half of the area. The post-layout simulated signal to noise and distortion ratio with 200 MHz input is 32.52 dB at 2 GS/s. The total power consumption is about 360 mW from a 1.8 V supply. The measured signal to noise and distortion ratios at 500 MS/s with 50 and 100 MHz input are 28.58 dB and 23.46 dB, respectively.
In addition to the design and implementation of a high speed flash ADC, the relation between the resistive averaging network and input signal frequency is analyzed. The analysis shows that the input frequency sets an upper bound for the ratio of the load resistance to the averaging resistance. With this bound, the high frequency performance of the proposed flash ADC is optimized.
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