Design of a Superscalar Processor Simulator Using Operation State Machine Model
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 93 === With the growth of the embedded system, the application-specific processor is an important port of the market. In designing a processor, in addition to have a good performance and low power consumption, it is also important to shorten the time-to-market. Ther...
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| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/14628002810163409965 |
| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 93 === With the growth of the embedded system, the application-specific processor is an important port of the market. In designing a processor, in addition to have a good performance and low power consumption, it is also important to shorten the time-to-market. Therefore, we need a retargetable modeling framework to rapidly explore and evaluate a candidate processor. The modeling technique of the framework needs to accurately capture complex processor behaviors and generate efficient simulators. In this thesis, we apply the Operation State Machine (OSM) model to design a popular superscalar processor. We also explain how to use the OSM model to model a superscalar processor. The generated simulator is a cycle-accurate simulator that can provide performance metric. It can offer both hardware and software developers a good reference.
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