A Low Cost Memory Built-in Self-Test Architecture and its Design Automation

• Main Authors: Sheng-Chih Shen, 沈聖智
• Other Authors: Kuen-Jong Lee
• Format: Others
• Language: en_US
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/14806777607741455477

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 93 === 　　In this thesis, a low cost memory built-in self-test architecture called the LCBIST architecture which has the features of high speed, high fault coverage, low test power consumption, and low area overhead is proposed. A design automation tool called the LCBIST synthesizer that can synthesize the LCBIST architecture so as to reduce the human errors and increase the productivity is also developed. 　　The LCBIST architecture can support the testing of the synchronous static RAM (SRAM), the synchronous dynamic RAM (SDRAM) and the double data rate SDRAM (DDR SDRAM). Multiple memories can be tested in parallel using a single controller and hence the test area overhead is small. We also prove that the test application time of this architecture in the parallel mode is the minimum when only a single test pattern generator is used. With some special design techniques, the LCBIST architecture can achieve a very high clock rate for the purpose of at-speed testing. To reduce the test power, the LCBIST synthesizer can also generate the BIST circuitry based on the memory test scheduling results. In addition, a Gray code based address generator that can effectively reduce the power consumption of the address signal related circuits is also developed. Finally, multiple algorithms can be easily implemented in the LCBIST architecture to achieve the best fault coverage. 　　The LCBIST architecture has passed a set of IP qualification rules and is well suitable for a reusable design. For the coding part, the design rule checker, nlint, shows that our LCBIST architecture has no errors and no warnings, which indicates that the quality of the hardware description language (HDL) coding style is good enough. For the verification part, the code coverage of our test bench for the statement and branch tests are 100%, and that for the toggle test is 100% excepting for those constant value signals. Thus the quality of the verification procedure is also satisfactory.