| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 93 === Designing a complex system-on-a-chip (SoC) poses many challenges, such as the integration and reusability of silicon IPs and the scalability of a system. The Networks-on-a-Chip (NoC) is a good solution for these challenges. The adaptive Networks-on-Chip (aNoC) is a template of tiled-architecture consisting of numerous reconfigurable processor cores connected through a structured on-chip interconnection network. Using an interconnection network removes the limit of scalability of bus architecture.
However, routing data through an interconnection network can cause the cost of dedicated bandwidth, longer latency, increased area, and higher power consumption. This thesis covers the design issues of the on-chip network of the NoC template, and the design and implementation of a router for the on-chip interconnection network of the template. The proposed router adopts a new switching algorithm to accomplish the maximal usage of channels, and the routing module of the router can be easily modularized according to different routing algorithms adopted in the router. The way of transmitting packets by wormhole, virtual channel and pipeline can achieve the fast data transfer and release the overhead of extending the NoC system.
The proposed router was developed as an IP of NoC which can be easily modularized for users adopting different number of ports, virtual channels, channel width, buffer size and different routing (including dynamic and static routing) and arbitration algorithms. The benchmark router with 5 ports, each port constants 4 32-bit virtual channels, can operate at 200MHz and the bandwidth can be up to 1.6Gbps. The performance of the router is enough for an HDTV application on NoC.
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