| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 93 === As the technology scales to subtle feature sizes, the integration of more heterogeneous components into a System-On-a-Chip becomes inevitable. To guarantee correct operation of a system, because the clock skew will affect the performance of the system. In many practical applications, the Phase-Locked Loop (PLL) is recognized as one of the important components for clock recovery. As the system operates at higher and higher frequency, factors like clock jitter become crucial in PLLs.
Conventionally, jitter is measured by using externally expensive Automatic Test Equipment (ATE). In this thesis, we propose an on-chip circuit to measure the jitter. The measurement circuit is based on the VDL architecture and it possesses the multi-resolution function, which can be used to measure different jitter quantity resulted from different jitter sources. Moreover, the self-referenced signal technique is adopted in the measurement circuit. The jitter value is translated to digital signal by the on-chip measurement circuit for output analysis. The operating frequency of the measurement circuit in this thesis is 100MHz with the measurement range being 1.68ns in fine-tune procedure (30ps) and 5ns in coarse-tune procedure (250ps). The measurement circuit is simulated using the TSMC 0.35um 2P4M technology.
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