| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 93 === With the fast development of modern industry, electricity demand is seen highly increased nowadays. The provision of electric power of high quality is thus deemed more important, hence motivating the study of this thesis that is aimed at solving the state estimation with a more efficient strategy. Based on such a goal, the hardware realization of state estimation is proposed where the field programmable gate array (FPGA) integrated with the concept of system-on-a-chip is employed. Meanwhile, the PCI bridge circuit as well as the Nios II processor is also combined in the proposed structure with the anticipation of reaching a state estimation system suitable for the PCI bus. The proposed system has been tested through the simulation validation. Test results have confirmed that the proposed approach is capable of grasping the states of a power system, which would be also beneficial for the increment of power system reliability, ensuring a supplying power of high quality.
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