| Summary: | 碩士 === 國立中興大學 === 電機工程學系 === 93 === Recently, as the fabrication technology advances, combining with the increasing computational capability of processor, there is growing interest in the use of chip-to-chip serial links technology. The research of this thesis focuses on designing a high-speed serial link system. It is divided into four parts.
First, the first part of this text discusses some basic issues for the link, for example, channel modeling and signaling noise source.
The second part describes the design of the phase-locked loop (PLL) and the delay-locked loop (DLL). The building blocks of the PLL and the DLL are introduced, and the design issues of them include bandwidth requirement, jitter performance, and locked time are elucidated. Some commonly used circuits of the phase detector, the charge pump, the voltage-controlled oscillator and the voltage-controlled delay line are classified.
In the third part, a clock and data recovery (CDR) circuit using the new phase detector has been developed. Unlike the conventional Hogge’s phase detector, the proposed detector has low output jitter and wide capture range characteristics. The CDR has been fabricated by 0.35-um N-well CMOS process and the active area occupies 750um*900um. When the input data rate is 1-Gb/s, the measured rms and peak-to-peak jitters for the recovered clock are 17.94-ps and 120-ps, respectively. And the measured rms and peak-to-peak jitters for the retimed data are 29.88-ps and 170-ps, respectively. The power consumption is 64.8-mW in the locked state at a 3.3-V supply voltage.
Finally, an efficient I/O employing the pulse-width-modulation (PWM) and pulse-amplitude-modulation (PAM) techniques is presented. In contrast with conventional techniques, it is implemented to effectively push high data rates through bandwidth-limited channels. The symbol rate is 250-MHz which corresponds to an equivalent data rate of 1-Gb/s. By experimental results, the measured peak-to-peak jitters for the transmitter output is 160-ps. And the recovered clock has a peak-to-peak jitters of 136-ps at 250-MHz, the retimed data has a peak-to-peak jitters of 150-ps at 250-Mb/s. The occupied die area is 867um*996um for the transmitter and 1800um*1800um for the receiver. The transmitter and receiver power consumption is 86-mW and 45-mW, respectively.
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