Low-Complexity IEEE 802.11a/b/g Wireless LAN MAC Layer IP Design on Ad-hoc Mode: Receiver Part
碩士 === 國立中興大學 === 電機工程學系 === 93 === In the modern life, various kinds of communication technology have occupied quite important position. In computer communication, with the formulation of the 802.11x series specification of IEEE, the research and development of the wireless network is hotter and ho...
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ndltd-TW-093NCHU04420732016-06-08T04:13:34Z http://ndltd.ncl.edu.tw/handle/86419686616790818142 Low-Complexity IEEE 802.11a/b/g Wireless LAN MAC Layer IP Design on Ad-hoc Mode: Receiver Part 低複雜度Ad-hoc模式IEEE802.11a/b/g無線區域網路媒體存取控制層IP設計:接收器部分 Jia-Wei Jhang 張家偉 碩士 國立中興大學 電機工程學系 93 In the modern life, various kinds of communication technology have occupied quite important position. In computer communication, with the formulation of the 802.11x series specification of IEEE, the research and development of the wireless network is hotter and hotter. Under the stream that the electronic equipment moves towards the trend of the smaller volume and less power consumption, embedded system, SoC design has developed gradually. The most popular CPU in this stream is ARM CPU that was issued by ARM Company. By applying ARM BUS, The integration of IP is more convenient. And higher performance and lower power consumption that ARM CPU offer let the device that engineers designed has more battery life. This thesis proposes a design that can be applied on 802.11 MAC (Medium Access Control) layer. Our purpose is designing a structure that can work with many different physical layers (PHY) like 802.11 a/b/g standard. This design is high modulize. It’s divide the function of MAC into Frame Decoding, Timing synchronization, CRC Checking, Control Logic , and AHB wrapper. We also divide the Frame Decoding module into several smaller block, all decoding block have an enable signal, which is controlled by control logic that controls whole frame decoding progress. The modulized design let function modifying is simpler if it’s needed in the future. We just only adjust sub module to fit our need. We have built a register file between transmitter and receiver for those frame that need reply in real time can be processed immediately. Beside co-work with other IPs, The AHB (Arm Highspeed Bus) compatibility lets our design more simple and efficient by applying the high performance and HW/SW interface that provided by ARM core. In hardware connection part , we implement Ad-Hoc mode first. Ad-Hoc mode is usually using in local connection between several wireless devices. The operation of this mode is easier to understand and more flexible. It’s the basic connection method in WLAN. The basic procedure flow of connection controlling is built in the hardware part. Authentication and management function is implemented by software. Base on Ad-Hoc connection, we implement DCF transmittion algorithm on it. Finally, we adopting the software “Seamless”. This software can execute hardware/software co-verification. We use it to make sure that our design can work on AHB and decode MAC frame correctly. Chie-Peng Fan 范志鵬 2005 學位論文 ; thesis 61 zh-TW |
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碩士 === 國立中興大學 === 電機工程學系 === 93 === In the modern life, various kinds of communication technology have occupied quite important position. In computer communication, with the formulation of the 802.11x series specification of IEEE, the research and development of the wireless network is hotter and hotter. Under the stream that the electronic equipment moves towards the trend of the smaller volume and less power consumption, embedded system, SoC design has developed gradually. The most popular CPU in this stream is ARM CPU that was issued by ARM Company. By applying ARM BUS, The integration of IP is more convenient. And higher performance and lower power consumption that ARM CPU offer let the device that engineers designed has more battery life.
This thesis proposes a design that can be applied on 802.11 MAC (Medium Access Control) layer. Our purpose is designing a structure that can work with many different physical layers (PHY) like 802.11 a/b/g standard. This design is high modulize. It’s divide the function of MAC into Frame Decoding, Timing synchronization, CRC Checking, Control Logic , and AHB wrapper. We also divide the Frame Decoding module into several smaller block, all decoding block have an enable signal, which is controlled by control logic that controls whole frame decoding progress. The modulized design let function modifying is simpler if it’s needed in the future. We just only adjust sub module to fit our need. We have built a register file between transmitter and receiver for those frame that need reply in real time can be processed immediately. Beside co-work with other IPs, The AHB (Arm Highspeed Bus) compatibility lets our design more simple and efficient by applying the high performance and HW/SW interface that provided by ARM core. In hardware connection part , we implement Ad-Hoc mode first. Ad-Hoc mode is usually using in local connection between several wireless devices. The operation of this mode is easier to understand and more flexible. It’s the basic connection method in WLAN. The basic procedure flow of connection controlling is built in the hardware part. Authentication and management function is implemented by software. Base on Ad-Hoc connection, we implement DCF transmittion algorithm on it. Finally, we adopting the software “Seamless”. This software can execute hardware/software co-verification. We use it to make sure that our design can work on AHB and decode MAC frame correctly.
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author2 |
Chie-Peng Fan |
author_facet |
Chie-Peng Fan Jia-Wei Jhang 張家偉 |
author |
Jia-Wei Jhang 張家偉 |
spellingShingle |
Jia-Wei Jhang 張家偉 Low-Complexity IEEE 802.11a/b/g Wireless LAN MAC Layer IP Design on Ad-hoc Mode: Receiver Part |
author_sort |
Jia-Wei Jhang |
title |
Low-Complexity IEEE 802.11a/b/g Wireless LAN MAC Layer IP Design on Ad-hoc Mode: Receiver Part |
title_short |
Low-Complexity IEEE 802.11a/b/g Wireless LAN MAC Layer IP Design on Ad-hoc Mode: Receiver Part |
title_full |
Low-Complexity IEEE 802.11a/b/g Wireless LAN MAC Layer IP Design on Ad-hoc Mode: Receiver Part |
title_fullStr |
Low-Complexity IEEE 802.11a/b/g Wireless LAN MAC Layer IP Design on Ad-hoc Mode: Receiver Part |
title_full_unstemmed |
Low-Complexity IEEE 802.11a/b/g Wireless LAN MAC Layer IP Design on Ad-hoc Mode: Receiver Part |
title_sort |
low-complexity ieee 802.11a/b/g wireless lan mac layer ip design on ad-hoc mode: receiver part |
publishDate |
2005 |
url |
http://ndltd.ncl.edu.tw/handle/86419686616790818142 |
work_keys_str_mv |
AT jiaweijhang lowcomplexityieee80211abgwirelesslanmaclayeripdesignonadhocmodereceiverpart AT zhāngjiāwěi lowcomplexityieee80211abgwirelesslanmaclayeripdesignonadhocmodereceiverpart AT jiaweijhang dīfùzádùadhocmóshìieee80211abgwúxiànqūyùwǎnglùméitǐcúnqǔkòngzhìcéngipshèjìjiēshōuqìbùfēn AT zhāngjiāwěi dīfùzádùadhocmóshìieee80211abgwúxiànqūyùwǎnglùméitǐcúnqǔkòngzhìcéngipshèjìjiēshōuqìbùfēn |
_version_ |
1718297662026940416 |