| Summary: | 碩士 === 國立中興大學 === 電機工程學系 === 93 === To constitute a complete transceiver for modern wireless communication systems, the frequency synthesizer which generates the local oscillator (LO) signal is an indispensable building block. Wherever frequencies are translated, frequency synthesis is crucial to provide clean, stable and programmable LO signals. The phase-locked loop (PLL) is used for a frequency synthesizer in almost all wireless communication chipsets on the market.
In order to implement a fractional-N frequency synthesizer, we need compensation techniques. However, it would cause problems when the division ratio of the frequency divider switches between two integers, it would increase the phase noise in a feedback network. Even if we can decrease it with noise shaping of PLL characteristic by using oversampling-modulator technique, it may still cause quantization error.
In this thesis, we develop a new fractional-N frequency divider architecture to improve the above-mentioned limitation with the aid of a phase compensated technique. Because of the constant division ratio, the phase noise problem in frequency divider could be reduced. The new high-frequency fractional–N frequency divider with a phase compensation technique can be operated with input signal frequency ranging at least from 3G Hz to 4G Hz, and achieve the divide ratio of N + (f / 16). The on-chip phase compensation by a delay-locked loop (DLL) is adopted to reduce the fractional spurs in the fractional-N frequency synthesizer. The experiments prove the chip to work properly.
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