| Summary: | 碩士 === 國立中興大學 === 電機工程學系 === 93 === Recently, the applications of finite field is widely applied in many areas, such as error correcting codes, cryptography, and computer science. Multiplication has large complexity and enormous time consuming among the basic arithmetic operations in finite field multiplier. Therefore, to choose a finite field multiplier
with simple architecture and high efficiency is necessary.
The complexity of finite field multiplier is closely related to the choice of a basis in finite field. The selection of finite field bases results in different construction and complexity for the multiplier. We will study the Massey-Omura multiplier over normal bases and propose some variations of it. The finite field multipliers
can be roughly classified into two categories: bit series multiplier and bit parallel multiplier. The main difference between bit series and bit parallel multipliers is their area and time complexity. Though the area complexity of bit series multiplier is lower than bit
parallel multiplier, the time complexity of bit series multiplier is increased. On the other hand, bit parallel multiplier has higher area complexity with high speed. The redundancy problem and
redundancy construction of bit parallel multiplier over normal
basis will be addressed in the paper. We will discuss two previous constructions and proposed two new normal basis multipliers. The area complexity of two new bit parallel multipliers can be reduced by the redundancy of key function and we can trade off the area complexity and time complexity.
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