| Summary: | 碩士 === 國立高雄應用科技大學 === 電機工程系碩士班 === 93 === This thesis is major research of the application of a CMOS low noise amplifier (LNA) for MBOA group1. The chip is realized in TSMC standard 0.18um CMOS process. After measuring, the LNA chip at frequency 4GHz exhibits an input return loss of 7.1 dB, output return loss of 9 dB, gain of 10.6dB, noise figure of 5.6dB, output P1dB of –14dBm, OIP3 of –3dBm and power consumption of 12mW.
Besides, this thesis also research on the correct method which employs about the SMA terminal and 1.0mm PCB. After studying,we could get a method that employed the terminal of SMA to achieve 50Ω and the skills of PCB layout.
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