| Summary: | 碩士 === 崑山科技大學 === 電子工程研究所 === 93 === In this thesis, we propose a design of an accurate and high sampling rate current memory. The current memory performs very well in high accuracy, high sampling rate and high output resistance. The current memory cell uses a feedback amplifier to achieve high output resistance and accuracy. With transistor-only characteristics, it is suitable in mixed-signal applications. In this thesis we discuss the operation principle, characteristics of the proposed current memory. Non-idealities in current memory including clock feedthrough, drain-gate parasitic capacitive coupling errors, mismatch errors, input-output resistance errors, and settling errors are discussed in detail. These quality factors dominate the whole performance of the current memory. After that, this current memory is used in applications, such as a spline function generator (SFG), fuzzy controllers in a field programmable analog array (FPAA), and a interpolation based signal synthesizer, …, etc. The HSPICE results show that the performance of the current memory is superior to other current memories.
The whole chip was implemented using a TSMC 0.35μm 2P4M mixed-mode process technology. The current memory’s sampling rate is 50MHz, signal frequency input is 2.5MHz of amplitude 0~130μA, and the worst cases error is within 0.5μA.
|
|---|
