System Level Design and High Level Synthesis of Image Processor
碩士 === 義守大學 === 電機工程學系碩士班 === 93 === In this thesis, a modified high level synthesis methodology based on reference documents[1][2][3] is proposed, it effectively improves the low circuit performance caused by original methodology. This methodology proceeds from system analysis, use IDEF0 to set up...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/83538673413966868403 |